library ieee;
use ieee.std_logic_1164.all;
use work.mis_componentes.all;


entity allpract is
port(A,B,C,D,E:in std_logic;
	I,F,G,H:out std_logic);
	
end allpract;


architecture bhv of allpract is

begin

U1: pract1 PORT MAP (A=>A,B=>B,C=>C,D=>D,E=>E,I=>I);
U2: pract2 PORT MAP (A=>A,B=>B,C=>C,D=>D,E=>E,F=>F);
U3: pract3 PORT MAP (A=>A,B=>B,C=>C,D=>D,G=>G);
U4: pract4 PORT MAP (A=>A,B=>B,C=>C,D=>D,H=>H);

end bhv;